Wireless communication system requires synchronization processing for setting up synchronization between a base station side and a terminal side or between terminals. Such synchronization processing needs various correlation operation processings such as a first stage (timing correlation processing) and a second stage (code correlation processing) of cell search processing, and path search processing (timing correlation processing), for example. Timing correlation processing here represents processing of executing correlation processing with respect to the same correlation code (hereinafter, simply referred to as a code in some cases) at a plurality of timings to detect a peak, thereby detecting timing as a reference of a transmission/reception data signal. Code correlation processing here represents processing of executing correlation processing with respect to a plurality of correlation codes at obtained one reference timing to detect a peak, thereby detecting a desired code. Timing correlation processing and code correlation processing are in general realized by using a dedicated circuit such as a matched filter or a sliding correlator. However, since such correlation operation processing requires a large amount of arithmetic operation, efficient parallelization and speed-up of processing to be realized by sharing codes, data, correlators and the like are demanded.
Related art for solving the problem is recited in, for example, Patent Literature 1. Proposed in Patent Literature 1 is a technique of sharing each correlator with a synchronization processing circuit allowed to switch between a synchronization detection mode and a data detection mode. According to the related art recited in Patent Literature 1, a sliding correlator allowed to switch between the synchronization detection mode and the data detection mode is provided to execute correlation processing with respect to reception data signals by synchronization detection correlation coefficients of phases different from each other in the synchronization detection mode to detect correlation timing and after detecting the timing, switch to the data detection mode to execute correlation processing in a plurality of data spread sequences at the timing in question, thereby obtaining reception data.
While the related art recited in Patent Literature 1 has an advantage of effective use of each correlator by sharing the same in the synchronization detection mode and the data detection mode, however, because of the structure in which each correlator requires a code generator each for synchronization detection and data detection, when the number of kinds of corresponding codes is increased, the problems occur that rectification of as many circuits as the number of correlators is required and that the circuit scale will be increased in proportion to the number of correlators to result in having low efficiency and low expandability.
Other related art is recited, for example, in Patent Literature 2. Proposed in Patent Literature 2 is a technique for speed-up by dividing an entire phase range into four search ranges and allocating each search range to each of four complex correlator units at the time of capturing synchronization. Disclosed as related art in Patent Literature 2 is an example of a technique of speeding up synchronization set-up by allocating four synchronization search ranges to four complex correlators, respectively.
The related art recited in Patent Literature 2 also has the problems that the same spread code which differs only in phase is generated in each correlator unit and that since the circuit structure is dedicated for timing correlation processing, further sharing of the circuit with other code correlation processing and the like is difficult.
Further related art is recited, for example, in Patent Literature 3. Proposed in Patent Literature 3 is a technique of selecting a user code for each correlator set, selecting one of reception data signals at a plurality of antennas by each correlator in the correlator set and inputting the selected signal to execute restructuring for which antenna signal each correlator should execute correlation processing.
While the related art recited in Patent Literature 3 has an advantage that for which antenna signal each correlator should execute correlation processing can be restructured, a problem occurs that for obtaining the advantage, a selector which selects one of as many data reception signals as the number of antennas is required for each correlator, resulting in having an extremely large overhead in circuit scale. Further problem is that since a user code is input to each correlator set, when processing the same user code whose timing differs by a plurality of correlator sets, each user code should be generated individually.
Patent Literature 1: Japanese Patent Laying-Open No. 2006-203354
Patent Literature 2: Japanese Patent Laying-Open No. 2000-115148
Patent Literature 3: Japanese Patent Laying-Open No. 2007-104729.
First problem is that none of the above-described related art recited in Patent Literature 1 through 3 enables a synchronization processing circuit in a wireless communication system to cope with both timing correlation processing and code correlation processing efficiently.
The reason is that while for a wireless communication terminal to synchronize with a base station, cell search processing is required of detecting reception timing and a base station code from the base station, an enormous amount of arithmetic operation is required for simultaneously detecting both timing and a code. Therefore, generally employed is a method called multistage cell search, that is, a method of establishing synchronization with a base station in stages by detecting reception timing by timing correlation processing at a first stage and detecting a base station code by code correlation processing at the detected reception timing at second and third stages. Accordingly, sharing a synchronization processing circuit in the first and second (third stage) stages or in path search processing is crucial in terms of an effective use of the synchronization processing circuit (operating ratio). However, mounting both code generators on each correlator causes a large overhead in circuit scale, which is a disadvantage in efficient realization. In addition, since in timing correlation processing, in particular, the necessary amount of processing is enormous in general to invite further parallelization which needs speed-up.
Second problem is that the above-described related art recited in Patent Literature 1 through 3 fails to enable parallel execution of a plurality of synchronization processings by a synchronization processing circuit in a wireless communication system and fails to allow assignment of the number of correlation operation units to each synchronization processing to be changed.
The reason is that in general, synchronization processing requires an enormous amount of arithmetic operation in correlation operation in particular and since the faster a processing result can be obtained, the more improved is synchronization performance accordingly, it is better for cell search processing and path search processing or the like to be executed in parallel. Another reason is that if the number of correlation operation units that can be used in each synchronization processing executed in parallel is fixed, when any of required processing performances is improved or when efficient load distribution processing is required taking each required performance into consideration, the correlation operation units cannot be efficiently used with each other.
Third problem is that the above-described related art recited in Patent Literature 1 through 3 fails to flexibly cope with various kinds of synchronization processings in a plurality of radio systems.
The reason is that since contents and codes of synchronization processing in general largely depend on specification of each radio system and the required amount of arithmetic operation is relatively large, synchronization is realized by mounting a dedicated synchronization processing circuit for each radio system.
Along with improvement in a processing capacity caused by recent scale-up and speed-up of a system LSI or the like, realization of a general-purpose synchronization processing circuit will be demanded hereafter which is capable of coping with a plurality of radio systems by the same hardware circuit and efficiently coping with a plurality of radio systems called a multi-mode radio or a software defined radio (SDR). For the realization of a multi-mode radio (software defined radio) in particular, demanded is a technique of efficiently realizing a structure, with less overhead in circuit scale, which allows the number of correlation operation units that execute parallel processing to be changed according to a required processing performance of each synchronization processing by using the same circuit.